Digital circuits on an integrated circuit (IC) generally detect the logic states of input signals and provide output signals responsive thereto. Because output signals are often used as inputs to subsequent logic devices, the output signals must have sufficient voltage and current to drive the subsequent devices. A common practice is to buffer output signals by using transistors to ensure adequate output signal strength. However, providing each output signal with its own output buffer and driver, supplied by a power supply can create noise problems when many outputs switch state at once. For example, when several output buffers switch from one binary state to another, the output buffers and drivers tend to draw significant current (even CMOS buffer and drivers tend to draw current when the buffers switch states), which in turn tends to cause, through the inductance of the package of the IC, significant noise from the switching of signals on the output conductors of the package. Moreover, the reference voltages, such as V.sub.cc and V.sub.ss, supplied on the IC tend to deviate from their normal voltage levels when many outputs switch state at once. These problems increase when the switching rate of operation for the buffers and drivers, or the number of buffers and drivers that are switching, increases; that is, when the frequency of the switching increases, more noise results and more deviations of V.sub.cc and V.sub.ss (from normal voltage levels) also results.
A solution for these problems in the prior art has involved the use of slew rate control for the output buffers. The control of slew rate allows a designer of an IC to slow the speed of an IC (when high speed is not necessary) by driving the buffers with less current. In turn, this reduces the noise generated by the IC and also tends to reduce the voltage deviations for the IC's internal reference voltages (as well as the effect on the off-chip power supply reference voltages). However, this solution is generally based on a chip designer's assumption of a worst case scenario for the number of output buffers which will be switching. This slew rate control in the prior art is independent of the number of outputs which may be switching at any one time.
Therefore, it is desirable to provide an output buffer control device that provides better slew rate control for several output buffers, and allows the designer or chip user to reduce noise, power consumption, or increase speed, without sacrificing performance.